A processing node or core in a computing system may be placed in any of multiple performance states (also referred to as power states or operational states) during operation, where the particular performance state (P state) is characterized by an associated operating voltage and operating frequency. Typically, the decision to transition the processing node between performance states is made by the operating system (OS). Other high-level control software or a hardware controller such as a bridge circuit (e.g., northbridge) may also initiate a change in the performance state. One exemplary factor for determining the appropriate performance state of a processing node is the processor's utilization. Utilization is the ratio of the time spent by one or more processing nodes in the active (execution) state to the overall time interval over which the execution time was tracked or measured. A higher node utilization may trigger the selection of a higher operating voltage and/or frequency to better address performance/watt requirements. For example, if the processing node is running at a relatively low performance state resulting in longer code execution time, the system perceives the need for a higher utilization and changes the processing node to a higher performance state suitable for faster code execution. Other suitable factors may cause the system to change performance states, such as the number of chip components running, the number or type of programs running, power saving needs, and/or performance needs, for example.
FIG. 1 illustrates an exemplary known computing system 10 including a computer processor 50. Processor 50, which may include one or more processing devices, includes one or more processing cores (nodes) 16, a bridge circuit 14, memory 19 containing microcode 21, and voltage/clock regulators 20. Memory 13 containing operating system code 15 is accessed by processor 50. In one embodiment, processing cores 16 execute microcode 21 and operating system code 15. In particular, an operating system module 12 includes operating system code 15 executed by at least one processing core 16, and microcode module 18 includes microcode 21 executed by at least one processing core 16. Processor 50 may include a central processing unit (CPU), a graphics processing unit (GPU), an accelerated processing unit (APU), and/or any other suitable processor or processing device. Processor 50 may be a single chip device, such as a system on a chip (SOC), or multiple physical devices. Computing system 10 includes a display 34 operatively coupled to processor 50. An exemplary computing system 10 includes a laptop, desktop, gaming system, mobile device (e.g., tablet, smartphone, etc.), multimedia player, electronic book (e-books), or any other suitable computing system or device.
Microcode module 18 interfaces with operating system module 12 to control aspects of processing cores 16. Microcode module 18 receives instructions or sequences from operating system module 12 and outputs instructions/sequences to bridge circuit 14 for controlling cores 16. For example, microcode module 18 provides signals to bridge circuit 14 for controlling the P state of processing cores 16 based on instructions from operating system module 12. Bridge circuit 14 manages communication between components of computing system 10, including between microcode module 18 and voltage/clock regulators 20. Bridge circuit 14 includes P state control logic 24 for controlling the P state of processing cores 16 based on instructions from microcode module 18.
Operating system module 12 (or P state control logic 24) may determine that a P state of processing cores 16 should change from one level to another based, for example, on usage or utilization of the cores 16. Operating system module 12 generates a P state change request 22 and transmits the request 22 to microcode module 18. Alternatively, operating system module 12 may write request 22 to a register, and microcode module 18 retrieves the request 22 from the register. The P state change request 22 identifies a target performance state, which includes a target operating voltage and a target operating frequency of the cores 16. Microcode module 18 sends the P state change request 22 to bridge circuit 14 for servicing. Microcode module 18 may adjust the request 22, for example, by delaying transmission of the request 22 to bridge circuit 14 or by transmitting the request 22 according to a delivery sequence.
Microcode module 18 writes the request 22 to a storage register 26 of bridge circuit 14 accessible by P state control logic 24. P state control logic 24 issues a voltage and frequency request 30 to regulators 20 (voltage regulator 40 and clock regulator 42, respectively) corresponding to the P state identified with request 22. The voltage and frequency request 30 specifies the target operating voltage and operating frequency of processing cores 16 that was identified in the request 22. Voltage/clock regulators 20 execute the voltage/frequency request 30 by sending corresponding voltage/frequency signals to the respective power rail and clock rail of processing cores 16. In response to the request 22 from microcode module 18, P state control logic 24 may implement the voltage change before or after the frequency change.
If computing system 10 is hacked or otherwise accessed without authorization, the hacker may attempt to cause processor 50 (or subsystems of processor 50) to enter into an improper P state with improper operating voltage and/or frequency levels of processing cores 16. Such improper operating voltages and frequencies may create security vulnerabilities in computing system 10. For example, changes to the operating voltage or frequency of the processing cores 16 may be applied to other voltage planes, pins, or rails coupled to other subsystems of processor 50, including processor memory, for example. As such, if a change in an operating voltage and/or frequency occurs in an undesired manner, there may be a potential that either the processing cores 16 or other subsystems are put in a state that allows the readout of data from registers and memory locations. For example, a hacker may attempt to glitch (e.g., short-term fault) the operating voltage in a predictable way to cause the processor 50 to incorrectly branch or load data, read out proprietary information, or perform other illegal or improper operations.
Therefore, a need exists for methods and systems to provide improved monitoring and secure control during a performance state change of the processor to thereby reduce the likelihood of a security breach. Further, a need exists for methods and systems to improve the detection and blocking of unauthorized access during a performance state change.